In the semiconductor industry, the minimum feature sizes of microelectronic devices are approaching the deep sub-micron regime to meet the demand for faster, lower power microprocessors and digital circuits. The Si-based microelectronic technology is currently faced with major materials challenges to achieve further miniaturization of integrated circuit devices. A gate stack containing a SiO2 gate dielectric and a degenerately doped polycrystalline Si gate electrode, which has served the industry for several decades, will be replaced with a gate stack having a higher capacitance.
High-capacitance materials, known as high-k materials (where “k” refers to the dielectric constant of the material), feature a dielectric constant greater than that of SiO2 (k˜3.9). In addition, high-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO2, ZrO2) rather than grown on the surface of the substrates (e.g., SiO2, SiOxNy). High-k materials may, for example, incorporate metallic silicates or oxides (e.g., Ta2O5 (k˜26), TiO2 (k˜80), ZrO2 (k˜25), Al2O3 (k˜9), HfSiO (k˜5-25), and HfO2 (k˜25)).
In addition to the gate dielectric layer, the gate electrode layer also represents a major challenge for future scaling of microelectronic devices. The introduction of metal-containing gate electrodes to replace the traditional doped poly-Si gate electrode can bring about several advantages. These advantages include elimination of the poly-Si gate depletion effect, reduction in sheet resistance, better reliability and potentially better thermal stability on the advanced high-k dielectric materials. In one example, switching from poly-Si to a metal-containing gate electrode can achieve a 2-3 Angstrom (Å) improvement in the effective or electrical thickness of the gate stack. This improvement occurs largely because the problem of poly-Si depletion at the interfaces with other materials is removed entirely.
Work function, resistivity, and compatibility with complementary metal oxide semiconductor (CMOS) technology are key parameters for the new gate electrode materials. One of the material selection criteria for the metal-containing gate electrode is that the work function be tunable. The work function of a material is the minimum energy needed to remove an electron from a solid to a point immediately outside the solid surface. Positive-channel Metal Oxide Semiconductor (PMOS) and the Negative-channel Metal Oxide Semiconductor (NMOS) transistor gate electrodes require different gate materials be used for the gate electrode to achieve acceptable threshold voltages; the latter having a Fermi level near the silicon valence band (E˜4 eV), and the former having a Fermi level near the conduction band (E˜5.1 eV).
High-energy implantation of dopant ions (e.g., nitrogen ions) into a metal gate electrode layer in a gate stack has been previously researched in order to lower the work function. However, ion implantation methods that include exposing the metal layer to high-energy ions can damage the gate stack, for example cause charging damage of the dielectric layer that can increase the leakage current and decrease the reliability of the dielectric layer. The charging damage from exposure of high-energy ions is expected to increase as the minimum feature sizes get smaller and the different materials layers that form gate stacks get thinner. Therefore, new methods are needed for processing gate stacks and, in particular, new methods for tuning the work function of the gate stacks are needed.